SDG #137 Beginners FPGA Clock Implementation in VHDL

This is a practical entry point into FPGA work using a low cost Lattice MachXO2 development board and the free Lattice Diamond toolchain. Rather than starting with abstract tutorials, the design work is anchored to a real goal: the timekeeping and display section of a 10MHz GPSDO reference oscillator project, where an accurate 1Hz-derived clock and a multiplexed digit display are genuinely needed.

The VHDL side covers the fundamentals a beginner actually trips over. Clock division from the board’s oscillator down to usable seconds ticks, cascaded counters for seconds, minutes and hours with correct rollover behaviour, binary to seven segment decoding, and a multiplexing state machine that cycles digit enables fast enough to look continuous to the eye. Along the way there is useful discussion of synchronous design habits, why everything should be driven from a single clock edge rather than gated clocks, and how signal and process structure in VHDL maps to what the fitter actually builds in logic cells.

For anyone weighing up the MachXO2 as a first FPGA, the takeaway is that it is a sensible choice: small enough to be cheap, large enough for counters, display drivers and later GPSDO control logic, with non-volatile configuration so the design boots without an external flash chip. Lattice Diamond is workable but not especially friendly, and the project synthesis and programming steps shown here will save a newcomer a lot of guesswork.

Useful viewing if you have an idea of what you want to build in hardware but have only worked with microcontrollers up to now, since the differences in mindset become obvious very quickly.